ASICs

The programmability of a processor is a scale is all about flexibility and performance – something highly programmable and customizable is adaptable to all sort of situations, but often isn’t as fast. However, something that has a very specified compute pathway can go very fast, but can’t do much beyond that pathway. On the flexible side, we have FPGAs, that can be configured to do almost anything. On the fixed side, we have ASICs, such as fixed function hardware for AI. Somewhere in the middle is what’s called a ‘Structured ASIC’, which tries to combine as many benefits from the two.

Google Announces Cloud TPU v2 Beta Availability for Google Cloud Platform

This week, Google announced Cloud TPU beta availability on the Google Cloud Platform (GCP), accessible through their Compute Engine infrastructure-as-a-service. Using the second generation of Google’s tensor processing units...

8 by Nate Oh on 2/15/2018

Intel Shipping Nervana Neural Network Processor First Silicon Before Year End

This week at the Wall Street Journal’s D.Live 2017, Intel unveiled their Nervana Neural Network Processor (NNP), formerly known as Lake Crest, and announced plans to ship first silicon...

25 by Nate Oh on 10/18/2017

Google’s Tensor Processing Unit: What We Know

If you’ve followed Google’s announcements at I/O 2016, one stand-out from the keynote was the mention of a Tensor Processing Unit, or TPU (not to be confused with thermoplastic...

39 by Joshua Ho on 5/20/2016

The Rush to Bitcoin ASICs: Ravi Iyengar launches CoinTerra

Bitcoin is a topic at AnandTech we have carefully steered away from due to the ever changing state of the market and the opinions of that market. For...

52 by Ian Cutress on 8/27/2013

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