Intel MIC: 22nm, 50+ Cores, Larrabee for HPC Announced
by Anand Lal Shimpi on May 31, 2010 11:27 AM ESTLast week Intel announced the scrapping of its plans to bring Larrabee to a discrete graphics card. While the announcement was open ended enough to allow for the restart of the discrete GPU program, from what I’ve heard the bulk of Larrabee GPU folks have been transitioned to work on Intel’s integrated graphics as it becomes a major focus of the company.
Larrabee as an architecture is not dead however. Intel made it very clear that a variant of the architecture designed for High Performance Computing (HPC) applications was still on track. It’s called the Intel Many Integrated Core (MIC) architecture and it claims to leverage both Larrabee and Intel’s many core research projects. The first Intel MIC product (codenamed Knights Corner) will be built on Intel’s 22nm process and feature more than 50 cores. I’m guessing it’s too early to tell how many cores will yield once the chip is done and Intel doesn’t want to miss any targets so we get a conservative estimate today.
The 22nm requirement puts the earliest release for Knights Corner at 2011. I’ve also heard that none of the GPU specific features of Knights Corner have been removed. Whether that means we’ll see a revival of the discrete GPU project or not remains to be seen. Intel’s efforts on improving compatibility and testing for its integrated graphics program would definitely come in handy if the company chooses to pursue anything higher end.
Intel is stressing the ease at which customers can port existing x86 code to Knights Corner, an advantage that NVIDIA’s Tesla lacks. The low hanging fruit for Intel’s MIC architecture are those applications that are already highly parallel and are thread constrained on Xeon today. With minor adjustments they should see a good speedup from the move to MIC.
Assuming porting x86 to MIC x86 is as easy as expected, we should see a quicker ramp of MIC adoption in the HPC space than NVIDIA has seen with Tesla thus far.
Facebook
Twitter
RSS
4 Comments
View All Comments
codedivine - Monday, May 31, 2010 - link
Will it support SSE or LRBNI or both?Shining Arcanine - Monday, May 31, 2010 - link
These are meant to be many small weak cores, so as much as possible will likely have been removed from its instruction set. Full SSE support is likely not included, although some pieces of it might be.LarrabeeRules - Monday, May 31, 2010 - link
it will be Next Gen LrbNIKlinky1984 - Monday, May 31, 2010 - link
These many core CPUs could possibly be handy in a web/cloud setting where a lot of NoSQL databases just need something that can filter through an index, nothing that fancy. Having 50 - 100 of these could possibly be a boon. It just depends on how well each core really performs.